Often the algorithmic model becomes so large that it needs to be split into distinct code segments. And many a times a set of statements need to be executed over and over again in different parts of the model. Splitting the model into subprograms is a programming practice that makes understanding of concepts in VHDL to be simpler. Like other programming languages, VHDL provides subprogram facilities in the form of procedures and functions. The features of subprograms are such that they can be written once and called many times. They can be recursive and thus can be repeated from within the scope. The major difference between procedure and function is that the function has a return statement but a procedure does not have a return statement.
Types of Subprograms

VHDL provides two sub-program constructs:
Procedure: generalization for a set of statements.
Function: generalization for an expression.
Both procedure and function have an interface specification and body specification.
Declarations of procedures and function
Both procedure and functions can be declared in the declarative parts of:
 Entity
 Architecture
 Process
 Package interface
 Other procedure and functions
Formal and actual parameters
The variables, constants and signals specified in the subprogram declaration are called formal parameters.
The variables, constants and signals specified in the subprogram call are called actual parameters.
Formal parameters act as placeholders for actual parameters.

Concurrent and sequential programs
Both functions and procedures can be either concurrent or sequential
•Concurrent functions or procedures exists outside process statement or another subprogram
•Sequential functions or procedures exist only in process statement or another subprogram statement.