64-Point FT Chip
A fixed-point 16-bit word-length 64-point FFT/IFFT processor developed primarily for the application in an OFDM based IEEE 802.11a wireless LAN base band processor. The 64-point FFT is realized by decomposing it in to a two dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplication compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift and add operation. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The core area of this chip is 6.8mm². The average dynamic power consumption is 41mW at 20Mhz operating frequency and 1.8Volt supply voltage. The processor completes one parallel-to-parallel 64-point FFT computation in 23 cycles; it can be used for any application that requires fast operation as well as low power consumption.
A fixed-point 16-bit word-length 64-point FFT/IFFT processor developed primarily for the application in an OFDM based IEEE 802.11a wireless LAN base band processor. The 64-point FFT is realized by decomposing it in to a two dimensional structure of 8-point FFTs. This approach reduces the number of required complex multiplication compared to the conventional radix-2 64-point FFT algorithm. The complex multiplication operations are realized using shift and add operation. Thus, the processor does not use a two-input digital multiplier. It also does not need any RAM or ROM for internal storage of coefficients. The core area of this chip is 6.8mm². The average dynamic power consumption is 41mW at 20Mhz operating frequency and 1.8Volt supply voltage. The processor completes one parallel-to-parallel 64-point FFT computation in 23 cycles; it can be used for any application that requires fast operation as well as low power consumption.
