Each design unit – entity architecture, configuration, package declaration and package body is analyzed (compiled) and placed in design library. Libraries are generally implemented as directories and are referenced by logical names. In the implementation of VHDL environment, this logical name maps to a physical path to the corresponding directory and this mapping is maintained by the host implementation. However just like variables and signals before we can use a design library we must declare the library we are using by specifying the libraries logical name.
This is done in VHDL program using the library clause that has the following syntax
library identifier { , . . . } ;
In VHDL, the libraries STD and WORK are implicitly declared therefore the user programs do not need to declare these libraries. The STD contains standard package provided with VHDL distributions. The WORK contains the working directory that can be set within the VHDL environment you are using. However if a program were to access functions in a design unit that was stored in a library with a logical name
IEEE. Then this library must be declared at the start of the program. Most if not all vendors provide an implementation of the library IEEE with packages such as STD_LOGIC_1164.vhd as well as other mathematics and miscellaneous packages.
Once a library has been declared all of the functions procedures and type declarations of a package in this library can be made accessible to a VHDL model through a USE clause. For example, the following statements appear prior to the entity declaration.
Library IEEE;
USE IEEE.STD_LOGIC_1164.all;
When these declarations appear just before the entity design unit they are referred to as the context clause. The second statement in the above context clause makes all of the type definitions functions and procedures defined in the package std_logic_1164.vhd visible to the VHDL model. It is as if all of the declarations had been physically placed within the declarative part of the process that uses them. A second form of the use clause can be used when only a specific item such as a function called my_func in the package is to be made visible.
USE IEEE.STD_LOGIC_1164.my_func;
The USE clause can appear in the declarative part of any design unit. Collectively the library and the use clauses establish the set of design units that are visible to the VHDL analyzer as it is trying to analyze and compile a specific VHDL design unit.
When we first start writing VHDL programs we tend to think of single entity architecture pairs when constructing models. We probably organize our files in the same fashion with one entity description and the associated architecture description in the same file. When this file is analyzed the library and the use clauses determine which libraries and packages within those libraries are candidates for finding functions procedures and user defined types that are referenced within the model being compiled. However these clauses apply only to the immediate entity architecture pair! Visibility must be established for other design units separately.
There are three primary design units they are entity package declarations and configuration declarations. The context clause applies to the following primary design unit. If we start having multiple design units within the same physical file then each primary design unit must be preceded by the library and use clauses necessary to establish the visibility to the required packages. for example let us assume that the VHDL model shown in package example are physically in the same file. The statements
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
must appear at the beginning of each model. That is prior to the entity descriptions we cannot assume that because we have the statements at the top of the file they are valid for all design units in the same file. In this case if we neglect to precede each model with the preceding statements the VHDL analyzer would return with an error on the use of the type STD_LOGIC in the subsequent models because this is not a predefined type within the language but rather is defined in the package STD_LOGIC_1164.
Creating a library
- Step1: using a text editor it is necessary to create a package with the functions, procedures and types(if necessary a deferred constant). In the example shown we have created a package called bit_pack with two functions int2vec and vec2int which converts integer to vector and vice versa.
- Step2: analyze and test each of the functions separately before committing them to placement within the package.
- Step3: it is important to note that packages have two parts package declaration and package body. The function declaration is placed in package declaration and function body is placed in package body.
- Step4: create a library in name bitlib. This operation of creating a library is simulator specific.
- Step5: compile the package into the library bitlib. The cad tool documentation provides guidelines on compiling design units into a library.
- Step6: write any VHDL model to use the library. In the example given below we have specified the model for 74163 ic, which is a counter.
- Step7: the model must declare library bitlib and provide access to the package via the use clause
- Step8: test the model of counter to ensure the functionality properly.
