- Packages are useful in organizing the data and the subprograms declared in the model
- VHDL also has predefined packages. These predefined packages include all of the predefined types and operators available in VHDL.
- In VHDL a package is simply a way of grouping a collections of related declarations that serve a common purpose. This can be a set of subprograms that provide operations on a particular type of data, or it can be a set of declarations that are required to modify the design
- Packages separate the external view of the items they declare from the implementation of the items. The external view is specified in the package declaration and the implementation is defined in the separate package body.
- Packages are design unit similar to entity declarations and architecture bodies. They can be put in library and made accessible to other units through use and library clauses
- Access to members declared in the package is through using its selected name
Library_name.package_name.item_name
- Aliases can be used to allow shorter names for accessing declared items
Two Components to Packages
- Package declaration---àThe visible part available to other modules
- Package body --àThe hidden part
Package declaration
The Packages declaration is used to specify the external view of the items. The syntax rule for the package declaration is as follows.
· The identifier provides the name of the package. This name can be used any where in the model to identify the model
· The package declarations includes a collection of declaration such as
- Type
- Subtypes
- Constants
- Signal
- Subprogram declarations etc
- Aliases
- components
The above declarations are available for the user of the packages.
The following are the advantages of the usage of packages
All the declarations are available to all models that use a package.
· Many models can share these declarations. Thus, avoiding the need to rewrite these declarations for every model.
The following are the points to be remembered on the package declaration
· A package is a separate form of design unit, along with entity and architecture bodies.
· It is separately analyzed and placed in their working library.
· Any model can access the items declared in the package by referring the name of the declared item.
Constants in package declaration
The external view of a constant declared in the package declaration is just the name of the constant and the type of the constant. The value of the constant need not be declared in the package declaration. Such constants are called are called deferred constants. The actual value of these constants will be specified in the package body. If the package declaration contains deferred constants, then a package body is a must. If the value of the constant is specified in the declaration, then the package body is not required.
The constants can be used in the case statement, and then the value of the constant must be logically static. If we have deferred constants in the package declaration then the value of the constant would not be known when the case statement is analyzed. Therefore, it results in an error. In general, the value of the deferred constants is not logically static.
Subprograms in the package declaration
· Procedures and functions can be declared in the package declaration
· Only the design model that uses the package can access the subprograms declared in the package declarations
· The subprogram declaration includes only the information contained in the header.
· This does not specify the body of the subprogram. The package declaration provides information regarding the external view of the subprogram without the implementation details. This is called information hiding.
· For every subprogram declaration there must be subprogram body in the package body. The subprograms present in the package body but not declared in the package declaration can’t be accessed by the design models.
